NDLI: Power-on reset circuit for SoC with multiple I/O power supplies

Content Provider	IEEE Xplore Digital Library
Author	Burdia, D. Lazar, A. Lazar, L.-C. Alecsandrescu, I.-E.
Copyright Year	2011
Description	Author affiliation: Faculty of Electronics, Telecommunications and Information Technology, “Gh. Asachi” Technical University of Iasi, Iasi, Romania (Burdia, D.; Lazar, A.; Alecsandrescu, I.-E.) \|\| Institute of Computer Science, Romanian Academy-Iasi Branch, Iasi, Romania (Lazar, L.-C.)
Abstract	One significant requirement for portable devices implemented in System-on-a-Chip (SoC) technology is to perform safely under extreme voltage power supply scenarios. This paper presents an on-chip power-on reset (POR) circuit and an I/O power supply detection circuit, with low steady-state power consumption. The POR circuit evaluates both the digital core voltage supply (VDD) and the highest chip voltage supply (VCC), which can be either 2.5V or 3.3V. Our technique allows the I/O power supply monitoring to be performed independently from the core power supplies. The I/O power supply detection circuit has a fixed detection threshold and can detect both the rising and falling ramps of the supply voltage. The circuit can operate for any I/O supply voltage level ranging from 1.5V to 3.3V. Simulation results show very low steady state power consumption. As a result, the proposed POR circuit is suitable for low power applications and embedding in portable device systems.
Starting Page	1
Ending Page	4
File Size	808499
Page Count	4
File Format	PDF
ISBN	9781612849447
e-ISBN	9781612849430
DOI	10.1109/ISSCS.2011.5978691
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-30
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Low voltage Power supplies Photonic band gap Detectors Steady-state System-on-a-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Power-on reset circuit for SoC with multiple I/O power supplies

A low voltage auto-reconfigured power-on-reset/bandgap reference circuit

A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications

A bandgap reference circuit design for Power-on Reset related circuits

On-chip power-on reset strategy and I/O power supply detection for VLSI circuits

Low-voltage power-on-reset circuit with least delay and high accuracy

A CMOS bandgap reference with high PSRR and improved temperature stability for system-on-chip applications

Design of an outer-chip controllable and inner-chip adjustable voltage reference

Design of a low voltage band-gap reference circuit for OLED-On-Silicon

Power-on reset circuit for SoC with multiple I/O power supplies

Similar Documents

Power-on reset circuit for SoC with multiple I/O power supplies

A low voltage auto-reconfigured power-on-reset/bandgap reference circuit

A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications

A bandgap reference circuit design for Power-on Reset related circuits

On-chip power-on reset strategy and I/O power supply detection for VLSI circuits

Low-voltage power-on-reset circuit with least delay and high accuracy

A CMOS bandgap reference with high PSRR and improved temperature stability for system-on-chip applications

Design of an outer-chip controllable and inner-chip adjustable voltage reference

Design of a low voltage band-gap reference circuit for OLED-On-Silicon

Power-on reset circuit for SoC with multiple I/O power supplies