NDLI: FPGA implementation of a low-area/high-SFDR DDFS architecture

Content Provider	IEEE Xplore Digital Library
Author	Cardarilli, G.C. D'Alessio, M. Di Nunzio, L. Fazzolari, R. Murgia, D. Re, M.
Copyright Year	2011
Description	Author affiliation: Department of Electronic Engineering University of Rome Tor Vergata Via del Politecnico 1, 00133 Rome, Italy (Cardarilli, G.C.; D'Alessio, M.; Di Nunzio, L.; Fazzolari, R.; Murgia, D.; Re, M.)
Abstract	This paper describes the FPGA implementation of a low area and high Spurious Free Dynamic Range (SFDR) Direct Digital Frequency Synthesizer (DDFS). The proposed architecture derives from the one proposed in [1] and fits perfectly in modern FPGA having DSP Blocks and/or embedded multipliers. The DDFS model in [1] was modified in order to reduce further the ROM size by a factor of 2 without worsen the SFDR and was implemented on a XILINX Virtex 5 FPGA. In this work we show that using the proposed hardware architecture, it is possible to reach very high SFDR (more than 157 dB) without impacting on the area occupancy. In fact traditional LUT-based DDFS has an exponential relationship between the ROM size and the number of phase bits.
Starting Page	1
Ending Page	4
File Size	804716
Page Count	4
File Format	PDF
ISBN	9781612849447
e-ISBN	9781612849430
DOI	10.1109/ISSCS.2011.5978667
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-30
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Memory management Hardware Table lookup Field programmable gate arrays Read only memory Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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