NDLI: Design and Synthesis of a High-Speed Hardware Linked-List for Digital Image Processing

Content Provider	IEEE Xplore Digital Library
Author	Xu, Jinbo Dou, Yong Song, Jian Zhang, Yang Xia, Fei
Copyright Year	2008
Abstract	To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle scheme to reuse the memory space where the data have been deleted. In our work, the length of the linked-list is parameterized and can be reconfigured. The structure is mapped onto an FPGA chip. Experimental results show that our proposal works functionally well. Only few hardware resources are used and it consumes pretty low power. According to the length of the list, clock speed from 100MHzup to 200MHz is achieved. Compared with the software linked-list structure in PC, our proposal in FPGA achieves 170.4 times of speedup in average. Our design has been utilized into people tracking system successfully.
Starting Page	171
Ending Page	175
File Size	267848
Page Count	5
File Format	PDF
ISBN	9780769531199
DOI	10.1109/CISP.2008.338
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design digital image processing Target tracking Digital images FPGA Data structures target recognition and tracking Proposals Digital signal processing Hardware Recycling Hardware linked-list Field programmable gate arrays Signal design
Content Type	Text
Resource Type	Article

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