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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Magaz, B. Bencheikh, M.L. |
| Copyright Year | 2008 |
| Description | Author affiliation: Res. & Dev. Center, Algiers (Magaz, B.; Bencheikh, M.L.) |
| Abstract | A new structure for an efficient Field Programmable Gate Array, FPGA, implementation of the order statistics CFAR detector, based on the (N-K+1)-th maximum determination, is proposed. By showing that the determination of the K-th order out of N reference cells is equivalent to selecting the (N + 1 - K)-th maximum, the detector that uses N reference cells can be implemented using only (N-1) comparators and (N-1) inverters. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussed. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 234002 |
| Page Count | 4 |
| File Format | |
| ISBN | 9788372077578 |
| DOI | 10.1109/IRS.2008.4585737 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-21 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Telecommunications Research Institute |
| Subject Keyword | FPGA OS-CFAR Computer architecture Detectors Radar Logic gates Hardware Inverters Field programmable gate arrays Implementation |
| Content Type | Text |
| Resource Type | Article |
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