NDLI: A 77-GHz FMCW front-end with FPGA and DSP support

Content Provider	IEEE Xplore Digital Library
Author	Haderer, A. Wagner, C. Feger, R. Stelzer, A.
Copyright Year	2008
Description	Author affiliation: Inst. for Commun. & Inf. Eng., Johannes Kepler Univ., Linz (Haderer, A.)
Abstract	Recent advances in the development of semiconductors allow the realization of low cost 77-GHz radar front-ends suitable for automotive applications. The requirements on the angular resolution often force designers to implement antenna arrays. In the last decade the trend moves towards digital array processing instead of analog beamforming because of the availability of cheap digital signal processors (DSP). In the case of an n-element receive array, the system must be capable of processing n receive channels in parallel resulting in a big amount of data. Field programmable gate arrays (FPGA) deliver the processing power and flexibility to handle the collected data and allow, in conjunction with a DSP, the implementation of sophisticated signal processing algorithms. This paper deals with the implementation of a 77-GHz frequency modulated continuous wave (FMCW) prototype radar system. The system is designed for use in array processing applications, with a maximum of eight parallel receive channels. The functionality of the prototype system is demonstrated in an imaging application. With the help of a portal axis the radar is moved along a synthetic aperture in order to reconstruct the reflectivity map of the imaging area.
Starting Page	1
Ending Page	6
File Size	196384
Page Count	6
File Format	PDF
ISBN	9788372077578
DOI	10.1109/IRS.2008.4585708
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-21
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Telecommunications Research Institute
Subject Keyword	Radar cross section Radar Digital signal processing Radar imaging Sensors Field programmable gate arrays Synthetic aperture radar
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in