NDLI: Combined Partial Test Vector Reuse and FDR Coding for Two Dimensional SoC Test Compression

Content Provider	IEEE Xplore Digital Library
Author	Guang Sheng Ma JingBo Shao RuiXue Zhang
Copyright Year	2008
Description	Author affiliation: Coll. of Comput. Sci. & Technol., Harbin Eng. Univ., Harbin (Guang Sheng Ma; JingBo Shao)
Abstract	This paper proposes a novel approach to core based SoC test compression. Research works show that almost all the test vectors have the same part in common. Therefore there exists such a vector, from which parts of each test vector from the different test sets can be sought. Based on this, first we attempt to find a vector named overlapped vector which contains parts of each test vector and has shorter length than that of the sum of each test vector's length. Second the overlapped test vectors are further compressed utilizing frequency-directed run-length (FDR) coding. Due to the fact that the test application time is proportional to the length of test vector, our proposal achieves as short test time as possible. Experimental results demonstrate that the proposed method obtains reduced test application time and significant test data compression rate.
Starting Page	375
Ending Page	378
File Size	239705
Page Count	4
File Format	PDF
ISBN	9780769531120
DOI	10.1109/ICICSE.2008.93
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	test compression Test data compression Statistical analysis Educational institutions Compaction Proposals Circuit testing overlapped test vector partial test vector reuse Computer science Frequency Internet Frequency-Directed Run-Length (FDR) coding System-on-a-chip
Content Type	Text
Resource Type	Article

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