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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Napoles, J. Guzman-Miranda, H. Aguirre, M. Tombs, J.N. Mogollon, J.M. Palomo, R. Vega-Leal, A.P. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electron. Eng., Univ. of Seville, Seville (Napoles, J.; Guzman-Miranda, H.; Aguirre, M.; Tombs, J.N.; Mogollon, J.M.; Palomo, R.; Vega-Leal, A.P.) |
| Abstract | Trends show that next coming technologies will produce new generations of very large circuits, running at high clock rates. Some critical applications will have to be protected against the remaining radiation at sea level. This is especially important in aerospace applications because ionizing radiation produces corruption of the internal state. New design methods have to be introduced to assure circuits will tolerate the impact of single event effects (SEE). It is very important to be able to analyze which parts of the circuits are more critical and how the behavior of the global system is degraded when one part suffers a SEE. This paper presents the last functionalities added to the FT-UNSHADES system to extend the analysis to SETs and MBUs. As a result, the system can insert and analyze many fault types at a rate of 180 K faults per hour in a system with 2 million test vectors. |
| Starting Page | 213 |
| Ending Page | 216 |
| File Size | 4795629 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424419920 |
| DOI | 10.1109/SPL.2008.4547760 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-03-26 |
| Publisher Place | Argentina |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | System testing Single event upset Space technology Emulation Redundancy Very large scale integration Hardware Combinational circuits Circuit faults Flip-flops |
| Content Type | Text |
| Resource Type | Article |
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