NDLI: Implementation of convolutional encoder and Viterbi decoder using VHDL

Content Provider	IEEE Xplore Digital Library
Author	Wong, Y.S. Wen Jian Ong Jin Hui Chong Chee Kyun Ng Noordin, N.K.
Copyright Year	2009
Description	Author affiliation: Department of Computer and Communication Systems Engineering, Faculty of Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor, Malaysia (Wong, Y.S.; Wen Jian Ong; Jin Hui Chong; Chee Kyun Ng; Noordin, N.K.)
Abstract	This work focuses on the realization of convolutional encoder and adaptive Viterbi decoder (AVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2 using field-programmable gate array (FPGA) technology. This paper presents a 4-state, radix-2, hard decision AVD which has the ability to decode adaptively through different traceback length (TL). The performance of the implemented AVD is analyzed by using ISE 9.2 and MATLAB simulations. The AVD is targeted to a Xilinx XCV300PQ240–4 FPGA device for hardware realization. The decoder parameter TL can be reconfigured via the implementation of AVD, in accordance with the changing channel noise characteristics of the threshold signal-to-noise ratio (SNR), which is 6 dB. The synthesis results show that the reconfiguration parameter TL of 4 and 15 of AVD implementation has significant difference (>20% improvement) in FPGA device utilization. The results also show that the use of reconfiguration leads to a 28% area occupancy of slice usage improvement over a TL of 15 model compared to a TL of 4 model with tolerable loss of decode accuracy, in accordance with the bit error rate (BER) for real-time voice and video.
Starting Page	22
Ending Page	25
File Size	190820
Page Count	4
File Format	PDF
ISBN	9781424451869
DOI	10.1109/SCORED.2009.5443417
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-16
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Convolutional codes Bit error rate FPGA Adaptive arrays Viterbi decoder Decoding Convolutional encoder VHDL Viterbi algorithm Convolution Performance analysis Mathematical model Field programmable gate arrays Signal to noise ratio
Content Type	Text
Resource Type	Article

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