NDLI: Design and simulation analysis of nanoscale vertical MOSFET technology

Content Provider	IEEE Xplore Digital Library
Author	Saad, I. Lee, R.M.A. Riyadi, M.A. Ismail, R.
Copyright Year	2009
Description	Author affiliation: Computational Nanoelectronics Group (CONE), Faculty of Electrical Eng., Universiti Teknologi malaysia, 81300, Malaysia (Riyadi, M.A.; Ismail, R.) \|\| School of Engineering and Information Technology, Universiti Malaysia Sabah, 88999, Sabah, Malaysia (Saad, I.; Lee, R.M.A.)
Abstract	Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.
Starting Page	215
Ending Page	218
File Size	126166
Page Count	4
File Format	PDF
ISBN	9781424451869
DOI	10.1109/SCORED.2009.5443109
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-16
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Doping effect Doping CMOS process Dielectrics Planar MOSFET Analytical models Vertical MOSFET Dielectric Pockets MOSFET circuits CMOS technology Short channel effect Threshold voltage Nanoscale devices Silicon Performance analysis
Content Type	Text
Resource Type	Article

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