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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sangyoon Park Kyeongyuk Min Jongwha Chong |
| Copyright Year | 2009 |
| Description | Author affiliation: College of Information & Communications, Hanyang University, Seoul, 133-791, Korea (Sangyoon Park; Kyeongyuk Min; Jongwha Chong) |
| Abstract | In this paper, we propose a new Context-based Adaptive Variable Decoding (CAVLD) hardware architecture without memory fabrication for mobile process. Previous CAVLD hardware architecture consists of five step blocks and each block gets several bits from controller and Look-Up Tables (LUTs). Many researches on LUTs basically require Read Only Memory (ROM) or Random Access Memory (RAM) fabrication process which is difficult to be implemented in general mobile digital logic fabrication process. In this reason, the hardware architecture for CAVLD inevitably has large hardware area and high power consumption. This paper propose two techniques, which combines five steps into four steps and optimizes LUTs without embedded memory for reducing chip size. By adopting these two techniques, the memory size is reduced 15% and the processing time is reduced 33% compared with previous architectures. |
| Starting Page | 204 |
| Ending Page | 207 |
| File Size | 377121 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424445219 |
| DOI | 10.1109/ISCIT.2009.5341257 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-09-28 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fabrication Memory architecture Random access memory Read-write memory Hardware Automatic voltage control Table lookup Decoding Logic Read only memory |
| Content Type | Text |
| Resource Type | Article |
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