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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xinhong Hei Kai Zhao Weigang Ma Lei Wang Guo Xie |
| Copyright Year | 2013 |
| Description | Author affiliation: Sch. of Comput. Sci. & Eng., Xi'an Univ. of Technol., Xi'an, China (Xinhong Hei; Kai Zhao; Weigang Ma; Lei Wang) || Sch. of Autom. & Inf. Eng., Xi'an Univ. of Technol., Xi'an, China (Guo Xie) |
| Abstract | As a complex and time-critical system, railway interlocking system (RIS) is vital for the safe operation of a train in station. For the next generation RIS named Distributed Railway Interlocking System (DRIS), the synchronization issue between internal devices, which means the guarantee of a well-organized cooperation, plays an important role in ensuring trains' safety running. Therefore, as a prerequisite a clear depiction of the synchronization within DRIS is essential. To that end, a temporal interval centered describing method is proposed. Firstly, considering the time shortage in UML statechart, the temporal interval is introduced to achieve the temporal extension of UML statechart. Secondly, the temporal statechart model of the DRIS is constructed with the method above. Finally, a brief analysis of the execution of internals of DRIS is given based on the constructed model, and the timeline mechanism is adopted to graphically describe the synchronization of internals of the DRIS by the relations between temporal intervals of states depicted in timeline diagram. |
| Sponsorship | IEEE Beijing Sect. |
| Starting Page | 709 |
| Ending Page | 713 |
| File Size | 170582 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467360777 |
| e-ISBN | 9781467360791 |
| DOI | 10.1109/MAPE.2013.6689853 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Unified modeling language temporal interval DRIS Educational institutions synchronization Rail transportation Safety Synchronization Time factors Standards timeline mechanism statechart |
| Content Type | Text |
| Resource Type | Article |
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