NDLI: Design on micro power dissipation E/D NMOS reference source

Content Provider	IEEE Xplore Digital Library
Author	Yonggui Hu Gangyi Hu Dongmei Zhu Yun Xu Jingfeng Yu
Copyright Year	2007
Description	Author affiliation: Nat. Labs. of Analog Integrated Circuits, Chongqing (Yonggui Hu; Gangyi Hu; Dongmei Zhu; Yun Xu; Jingfeng Yu)
Abstract	In this study, a novel micro power dissipation E/D NMOS reference source circuit was presented. The circuit is simple in structure, but is practical. Compared with a traditional BiCMOS band-gap reference source, the micro power dissipation E/D NMOS reference source has a small static current, and eliminates the need of parasitic bipolar transistor and resistor. All you need to do is to add a depletion-mode N-MONFET process to a conventional P-well process technology. An E/D NMOS reference source circuit has been developed in 2 Vm silicon-gate self-aligned CMOS process technology. In the range -55 to 125degC, the static current measured was less than 2 muA, the voltage regulation measured was less than 2mV, and the temperature coefficient measured was less than 100ppm/degC.
Sponsorship	IEEE Beijing Sect.
Starting Page	1408
Ending Page	1411
File Size	3194901
Page Count	4
File Format	PDF
ISBN	9781424410446
DOI	10.1109/MAPE.2007.4393542
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Bipolar transistors Photonic band gap micro power dissipation MOS devices Temperature measurement Current measurement depletion-mode N-MOS transistor CMOS technology BiCMOS integrated circuits Power dissipation Virtual manufacturing E/D NMOS reference
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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