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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liu Biwei Chen Shuming Hu Xiao |
| Copyright Year | 2008 |
| Description | Author affiliation: Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Kuala Lumpur (Liu Biwei; Chen Shuming; Hu Xiao) |
| Abstract | Much effort has been made to estimate SER (Soft error rate) in combinational logic. However, little of them involve glitch reconvergence. In this paper, we discuss how to estimate SER in combinational logic when considering reconvergence. We present Boolean difference expressions for the sensitization condition of six reconvergence categories so that symbolic technique can be used to compute logical masking of reconvergence. We develop an equivalent glitch method so that STA (Static Timing Analysis) like pre- characterization method can be applied to compute electrical masking of reconvergence. Furthermore, latching window masking of reconvergence is discussed. Experiment results of ISCAS'85 benchmark circuit show that considering of reconvergence will cause overall 13.9% SER reduction. The time and memory cost of our method is moderate. And the average error of our method is 3.3% relative to SPICE. |
| Starting Page | 1015 |
| Ending Page | 1020 |
| File Size | 381733 |
| Page Count | 6 |
| File Format | |
| ISBN | 9780769531366 |
| DOI | 10.1109/AMS.2008.166 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-13 |
| Publisher Place | Malaysia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Error analysis SET Computational modeling Switches SER esitmation Circuit faults Asia Attenuation SPICE Logic Reconvergence Clocks |
| Content Type | Text |
| Resource Type | Article |
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