NDLI: A yield-enhancement strategy for binary-weighted DACs

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Stability of the quasi-periodic and periodic attractors constrained to the hyper-plane in a ring of three-coupled hard-type oscillators

Bifurcation analysis in a hybrid time delay system

One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source

DC and AC characteristics and modeling of Si SSD-nano devices

Conditional quasi maximum-likelihood receiver for clipped OFDM signals

On the usage of delayed-feedback in amplifiers

2-V CMOS current operational amplifier with high CMRR

Rail-to-rail OTA utilizing linear V-I conversion circuit using single channel MOSFETs for input stage

1.8 V.0.35 /spl mu/m CMOS wideband programmable gain amplifier

Analysis of coil parameter extraction methods for on-chip inductor design

Simulation of ferrites by SPICE

Compact model for a cantilever beam MEM contact switch

Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolution

A yield-enhancement strategy for binary-weighted DACs

Modeling finite-memory nonlinearity in unit DAC elements, binary storage channels, and BPSK data channels

Dithered subband coding with spectral subtraction

Gradient-based adaptive algorithm for minimum phase-all pass decomposition of an FIR system

Towards a hardware realization of time-frequency source separation of speech

Time division digital programmable OTA for cellular neural networks

Inverse elastic wave propagation modeling on CNN-UM architecture

A customizable tool for cellular nonlinear network simulation

A 1.9 GHz CMOS class E power amplifier with +29 dBm output power and 58% PAE

Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologies

A reconfigurable CMOS VCO with an automatic amplitude controller for multi-band RF front-ends

Improving capacitive drive capability of two-stage op amps with current buffer

Integrated low noise preamplifier for biologic-electronics interfaces

Switched current filter design with the use of integrators composed of equal size transistors

A behavioral model for the nonlinear on-resistance in sample-and-hold analog switches

A simple submicron MOSFET model and its application to the analytical characterization of analog circuits

Comparative study of MOST resistive configurations

An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique

6 bit 1 GHz CMOS silicon-on-insulator flash analog-to-digital converter for read channel applications

Design techniques for high performance CMOS flash analog-to-digital converters

Robust reconstruction of nonuniformly sampled signals

Efficient sine and cosine computation using a weighted sum of bit-products

Fixed-point implementation of a robust complex valued divider architecture

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Robustness improvement in binary cellular non-linear network architectures

On cellular neural network learning

A new CNN template for POAC peak enhancement

Design of clock generating fully integrated PLL using low frequency reference signal

Chaos-based high-EMC spread-spectrum clock generator

EMI performance of spread spectrum clock signals with respect to the IF bandwidth of the EMC standard

General impedance synthesizer using minimal configuration of switching converters

Stability analysis of complete two-stage power-factor-correction power supplies

Resistorless KHN biquad using an DDA (difference diffference amplifier) and two CCCIIs (controlled current conveyor)

A fully automated flowgraph analysis tool for Matlab

Hybrid genetic algorithm engine for high-speed floorplanning

SystemC/sup FL/: a formalism for hardware/software codesign

1.8-V second-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS technology

Higher order dynamic element matching by shortened tree-structure in delta-sigma modulators

Design of /spl Sigma//spl Delta/ modulators with reduced number of operational amplifiers

A DCT-domain postprocessor for color bleeding removal

Data partitioning for parallel implementation of real-time video processing systems

A flexible architecture for image reconstruction in H.264/AVC decoders

On the bifurcation properties of a class of differentiate mappings

Chaotic motion generation with applications to liquid mixing

Modeling using 1-D map of complex behavior in coupled chaotic circuits with intermittency

On the steady state behaviour of an n/sup th/-order class of nonlinear mappings

RC-load analysis of the downconversion mixer IIP2

A single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) class 12 applications

Low voltage LC-ladder Gm-C low-pass filters with 42-215 MHz tunable range

Variable-gain up-conversion mixer with current reuse for 5-GHz W-LAN applications

Metamorphic HEMT amplifier for K- and Ka-band applications

Switched-capacitor body-biasing technique for very low voltage CMOS amplifiers

1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth product

CMOS interface for differential capacitive transducers

A low voltage, high speed current mode sample and hold for high precision applications

Current-steering D/A converter based on triple tail cell

Optimised Montgomery domain inversion on FPGA

Real time vision by FPGA implemented CNNs

FPGA implementation of a general purpose HMM processor based on token passing algorithm

Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder

Systematic top-down design of A/D converters

Use of nonlinear Chua's circuit for on-line offset calibration of ADC

Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell

Sampling jitter and power supply interference in current-steering D/A converters

Innovation to overcome limitations of test equipment

Occluded face recognition using parts-based representation methods

A realization of FIR system for on-line writer recognition

An effective compression scheme for prediction errors on lossless image coding

Recognition of isolated words corrupted by impulsive noise

Background removal in dental panoramic X-ray images by the A-Trous multiresolution transform

A yield-enhancement strategy for binary-weighted DACs

Content Provider	IEEE Xplore Digital Library
Author	Ola Andersson, K. Vesterbacka, M.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Linkoping Univ., Sweden (Ola Andersson, K.; Vesterbacka, M.)
Abstract	One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.
File Size	139055
File Format	PDF
ISBN	0780390660
DOI	10.1109/ECCTD.2005.1522908
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-02
Publisher Place	Ireland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Digital control Energy consumption Costs Digital-analog conversion Computational modeling Linearity Switches Encoding Computational complexity
Content Type	Text
Resource Type	Article

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