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Content Provider | IEEE Xplore Digital Library |
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Author | Zhi Wang Shuming Chen Wei Liu |
Copyright Year | 2015 |
Description | Author affiliation: Coll. of Comput., Nat. Univ. of Defense Technol., Changsha, China (Zhi Wang; Shuming Chen; Wei Liu) |
Abstract | Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs. |
Starting Page | 376 |
Ending Page | 380 |
File Size | 275876 |
Page Count | 5 |
File Format | |
ISSN | 21579563 |
e-ISBN | 9781467376792 |
DOI | 10.1109/ICNC.2015.7378019 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-08-15 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | quantum multiplier Power demand Quantum computing reversible logic ancilla input Logic circuits Design methodology Logic gates garbage output Yttrium Adders |
Content Type | Text |
Resource Type | Article |
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