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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chih-Hao Chao Kai-Yuan Jheng Hao-Yu Wang Jia-Cheng Wu An-Yeu Wu |
| Copyright Year | 2010 |
| Abstract | Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher network bandwidth. However, the length of heat conduction path and power density per unit area increase as more dies stack vertically. Routers of NoC have comparable thermal impact as processors and contributes significant to overall chip temperature. High temperature increases the vulnerability of the system in performance, power, reliability, and cost. To ensure both thermal safety and less performance impact from temperature regulation, we propose a traffic- and thermal-aware run-time thermal management (RTM) scheme. The scheme is composed of a proactive downward routing and a reactive vertical throttling. Based on a validated traffic-thermal mutual-coupling co-simulator, our experiments show the proposed scheme is effective. The proposed RTM can be combined with thermal-aware mapping techniques to have potential for higher run-time thermal safety. |
| Starting Page | 223 |
| Ending Page | 230 |
| File Size | 1554924 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424470853 |
| e-ISBN | 9781424470860 |
| DOI | 10.1109/NOCS.2010.32 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-05-03 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Temperature run-time thermal management Power system management 3D NoC Telecommunication traffic 3D IC traffic-aware Delay thermal-aware routing Runtime throttling Network-on-a-chip Thermal management Power system reliability Safety Three-dimensional integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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