NDLI: Application of partial reconfiguration of FPGAs in image processing

Content Provider	IEEE Xplore Digital Library
Author	Raikovich, T. Feher, B.
Copyright Year	2010
Description	Author affiliation: Department of Measurement and Information Systems, Budapest University of Technology and Economics, Hungary (Raikovich, T.; Feher, B.)
Abstract	FPGA based hardware accelerators have been more and more widely used in different kind of applications. As compared to other solutions and the direct hardware implementation, the advantage of the FPGA devices is their flexibility that arises from their programmable nature. In addition to this, some FPGA devices also support partial dynamic reconfiguration. When general purpose processors and reconfigurable computational structures are used together, the most advantageous properties of both components can be utilized. Algorithms (searching, sorting, signal and image processing, etc.) that are implemented such way have achieved 100 times or 1000 times better performance. This paper introduces a Xilinx Virtex-5 FPGA based reconfigurable hardware accelerator system, which has been created mainly for image processing purposes. By using the partial reconfiguration capability of the FPGA, the execution units in the system can be quickly reconfigured.
Starting Page	1
Ending Page	4
File Size	295733
Page Count	4
File Format	PDF
ISBN	9781424479054
e-ISBN	9783981375404
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	VDE
Subject Keyword	image processing Image processing Pipelines FPGA hardware accelerator Finite impulse response filter Hardware partial reconfiguration Field programmable gate arrays Pixel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Partial Reconfiguration Bitstream Compression for Virtex FPGAs

Implementation of realtime pipeline-folding 64-tap filters on FPGA

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

Optimal MAC structures in an FPGA

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays

FPGA accelerator for real-time skin segmentation

Rapid prototyping of orthonormal wavelet transforms on FPGAs

An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform

Application of partial reconfiguration of FPGAs in image processing

Similar Documents

Partial Reconfiguration Bitstream Compression for Virtex FPGAs

Implementation of realtime pipeline-folding 64-tap filters on FPGA

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform

Optimal MAC structures in an FPGA

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays

FPGA accelerator for real-time skin segmentation

Rapid prototyping of orthonormal wavelet transforms on FPGAs

An Reconfigurable FIR Filter Design on a Partial Reconfiguration Platform

Application of partial reconfiguration of FPGAs in image processing