NDLI: 100 Gbit/s authenticated encryption based on quantum key distribution

Content Provider	IEEE Xplore Digital Library
Author	Muehlberghuber, M. Keller, C. Felber, N. Pendl, C.
Copyright Year	2012
Description	Author affiliation: Graz University of Technology, Institute for Applied Information Processing and Communications (IAIK), Inffeldgasse 16a, 8010, Austria (Pendl, C.) \|\| ETH Zurich, Integrated Systems Laboratory (IIS), Gloriastrasse 35, 8092, Switzerland (Muehlberghuber, M.; Keller, C.; Felber, N.)
Abstract	We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.
Starting Page	123
Ending Page	128
File Size	153194
Page Count	6
File Format	PDF
ISBN	9781467326575
e-ISBN	9781467326582
e-ISBN	9781467326568
DOI	10.1109/VLSI-SoC.2012.6379017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Serpent Authenticated encryption FPGA Throughput Encryption OCB AES GCM High-throughput architecture Authentication Hardware Pipelining Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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