NDLI: CMOS implementation of static threshold gates with hysteresis: A new approach

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CMOS implementation of static threshold gates with hysteresis: A new approach

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CMOS implementation of static threshold gates with hysteresis: A new approach

Content Provider	IEEE Xplore Digital Library
Author	Parsan, F.A. Smith, S.C.
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering, University of Arkansas, Fayetteville, USA (Parsan, F.A.; Smith, S.C.)
Abstract	This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive NULL Convention Logic (NCL) 4×4 pipelined multiplier is developed and simulated with each gate style. The results show that the new gate style offers 27% speed-up with only a 5% increase in area and almost the same energy consumption.
Starting Page	41
Ending Page	45
File Size	382871
Page Count	5
File Format	PDF
ISBN	9781467326575
e-ISBN	9781467326582
e-ISBN	9781467326568
DOI	10.1109/VLSI-SoC.2012.6379003
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption NULL Convention Logic NCL Switches Logic gates Static gate Registers CMOS integrated circuits Transistors Threshold gate Hysteresis CMOS gate design
Content Type	Text
Resource Type	Article

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