NDLI: Area-efficient single-stage configuration for implantable neural recording amplifiers based on back attenuation

Content Provider	IEEE Xplore Digital Library
Author	Nekoui, M. Sodagar, A.M. Ehsanian, M.
Copyright Year	2014
Description	Author affiliation: Res. Lab. for Integrated Circuits & Syst. (ICAS), K.N. Toosi Univ. of Technol., Tehran, Iran (Nekoui, M.; Sodagar, A.M.) \|\| Fac. of Electr. Eng., K.N. Toosi Univ. of Technol., Tehran, Iran (Ehsanian, M.)
Abstract	A new single-stage configuration is proposed for low-power low-noise amplifiers designed for neural recording applications. Employing an attenuator in the feedback loop around the amplifier, both upper and lower cut-off frequencies of the amplifier $(f_{CL}$ and $f_{CH})$ are realized using much smaller capacitances as compared with those used in other neural amplifiers available in the literature. This leads to both considerable reduction in the consumed silicon area and increase in the input impedance of the amplifier. Furthermore, the high-resistance nonlinear pseudo-resistor traditionally used to achieve a very small $f_{CL}$ is replaced by a transconductance attenuator. Designed and simulated in a 0.18-μm CMOS process, the amplifier consumes 19.8 μW from a 1.8-V supply.
Starting Page	396
Ending Page	399
File Size	791578
Page Count	4
File Format	PDF
ISBN	9781479923465
DOI	10.1109/BioCAS.2014.6981746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-22
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Attenuators neural interfacing attenuation Cutoff frequency Noise implantable microsystems Attenuation Neural recording amplifiers Frequency measurement Transconductance Gain
Content Type	Text
Resource Type	Article

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