NDLI: A compact, nano-power CMOS action potential detector

Content Provider	IEEE Xplore Digital Library
Author	Hiseni, S. Sawigun, C. Ngamkham, W. Serdijn, W.A.
Copyright Year	2009
Description	Author affiliation: Biomedical Electronics Group, Electronics Research Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, the Netherlands (Hiseni, S.; Sawigun, C.; Ngamkham, W.; Serdijn, W.A.)
Abstract	Real time action potential (AP) detection is an important requirement for development of fully implantable neuroprosthetic devices. We present an ultra low-power CMOS analog circuit for detection of APs embedded in a noisy signal. The proposed strategy isolates APs by detecting subsequently a positive and a negative spike of each AP. An AP is detected only if the positive spike is detected within a short period of time after the negative spike was detected. The proposed circuit has been designed to be implemented in AMIS 0.35 µm technology (I3T80) and has been verified in Cadence using RF spectre. The final circuit operates from a 1-V supply and consumes only 1.5 nA. The detector is verified by means of simulations with synthetic neural waveforms and is able to successfully detect APs in noisy signals.
Starting Page	97
Ending Page	100
File Size	643355
Page Count	4
File Format	PDF
ISBN	9781424449170
DOI	10.1109/BIOCAS.2009.5372074
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit technology ultra low-power Energy consumption Circuit simulation Neurons action potential detector Frequency estimation multichannel recordings low-voltage prosthetic devices CMOS analog integrated circuits Detectors Isolation technology biomedical signal processing CMOS technology extracellular recordings Circuit noise Neural prosthesis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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