NDLI: Determining error rate in error tolerant VLSI chips

Content Provider	IEEE Xplore Digital Library
Author	Breuer, M.A.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Breuer, M.A.)
Abstract	In the near future all die implementing high performance circuitry will contain hundreds of thousands of defects. Most companies will attempt to achieve useful levels of functionally good die using classical and enhanced fault tolerant and defect tolerant techniques. We advocate a new notion for yield enhancement called error tolerance that includes marketing chips that occasionally output errors. The quantity and quality of errors produced by a chip can be characterized several ways, such as by accuracy, error rate, and accumulation (retention). This paper focuses on test techniques for estimating error rate.
Sponsorship	IEEE Computer Soc. Test Technol. Tech. Council (TTTC) Centre for Very High Speed Microelectronic Systems, Edith Cowan Univ. Australia
Starting Page	321
Ending Page	326
File Size	152175
Page Count	6
File Format	PDF
ISBN	0769520812
DOI	10.1109/DELTA.2004.10068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-28
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Error analysis Integrated circuit interconnections Very large scale integration Hardware Logic design Manufacturing Logic testing Signal design Logic devices
Content Type	Text
Resource Type	Article

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Clique partitioning based integrated architecture synthesis for VLSI chips

A testing methodology for large scale hybrid VLSI

A control constrained test scheduling approach for VLSI circuits

Reconfiguration algorithm of fault-tolerant two-dimensional VLSI arrays

Consistency Checking for MOS/VLSI Circuits

Wirability of logic circuit packages in LSI and VLSI

Specification and verification of VLSI systems

Contrasts in Physical Design between LSI and VLSI

Logic implementation for VLSI

Determining error rate in error tolerant VLSI chips

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