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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Heller, W.R. |
| Copyright Year | 1979 |
| Description | Author affiliation: California institute of Technology (Heller, W.R.) |
| Abstract | The problems of designing and manufacturing systems made from integrated circuits have been changing rapidly as semiconductor technology has made greater circuit densities possible. Because of this rapid rate of change and the short time available for system design, it is essential to have reasonably accurate preliminary estimates of logic circuit counts, package sizes, and costs, as well as of design schedules. By preliminary, we mean prior to availability of circuit level system logic designs and/or prior to availability of partitioning, placement, and wiring aids to layout in a particular technology. The problem is complicated by the difference in difficulty between the predictability of wiring demand on packages with regular arrays of logic carriers and packages containing variably sized and shaped groups of logic circuits. Methods have been developed for preliminary estimation of wiring capacity in both these situations, and both methods and results will be discussed. |
| Starting Page | 95 |
| Ending Page | 100 |
| File Size | 574112 |
| Page Count | 6 |
| File Format | |
| DOI | 10.1109/CMPSAC.1979.762473 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1979-11-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic circuits Large scale integration Very large scale integration Integrated circuit packaging Costs Logic design Wiring Logic devices Computer aided manufacturing Semiconductor device packaging |
| Content Type | Text |
| Resource Type | Article |
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