NDLI: Low power unrolled CORDIC architectures

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2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)

Table of contents

3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation

A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter

A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS

A CMOS High Resolution Multi-Edge Delay Generator

A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

A design platform for flexible programmable DSP for automotive sensor conditioning

A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm

A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process

Adaptive Power monitoring for self-aware embedded systems

An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm

An ultra wide-band adaptive frequency divider for mm-wave PLL applications

Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs

Application of spread-spectrum techniques to class-E DC/DC converters: some preliminary results

Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

Carrier frequency and sampling rate offsets effect on sub 6 GHz Massive MIMO

Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI

A comparison of serial interfaces on energy critical systems

Design and evaluation of correlation accelerator in IEEE-802.11a/g receiver using a template-based Coarse-Grained Reconfigurable Array

Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA

Design of a hybrid multicore platform for high performance reconfigurable computing

Digital background calibration in continuous-time delta-sigma analog to digital converters

Empirical results on parity-based soft error detection with software-based retry

Evaluation of the vertical magnetic field generated by a spiral planar coil

Executing secured virtual machines within a manycore architecture

Fault tolerant Field Programmable Neural Networks

Fault-tolerant implementation of direct FIR filters protected using residue codes

Fixed pattern noise correction for wide dynamic range CMOS image sensor with Reinhard tone mapping operator

Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

A fully synthesized all-digital VCO-based analog-to-digital converter

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

High-efficiency peak-current-control non-inverting buck-boost converter using mode selection for single Ni-MH cell battery operation

Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications

How small and still effective a CMOS-SoC could ever be?

Inductorless and cross-coupled wideband LNA with high linearity

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Design of a highly linear, low noise, broad band up-converter for cognitive radio applications

Long-Term ECG monitoring with zeroing Compressed Sensing approach

Low power, highly stable and wideband LNA for GNSS applications in SiGe technology

Low power unrolled CORDIC architectures

Microcontroller energy consumption estimation based on software analysis for embedded systems

A NAND gate based standard cell VCO for use in synthesizable ADCs

A new current stimulator architecture for visual cortex stimulation

A noise coupled ΣΔ architecture using a Non Uniform Quantizer

On-chip spatial filter for subretinal implants

Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems

Process tolerant highly linear mixer output stage with feedforward linearity improvement method for a high-IF converter

Secured-by-design FPGA: look-up tables and switch-boxes

Self-biasing high-voltage driver based on standard CMOS with an adapted level shifter for a wide range of supply voltages

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits

Single chip wireless condition monitoring of power semiconductor modules

System level design of a continuous-time ΔΣ modulator for portable ultrasound scanners

Systematic frequency planning for a high SFDR digital-IF RF-DAC-based transmitter

Test-driven modeling of embedded systems

The low delay low-pass FIR digital differentiators having flat passband and equiripple stopband

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator

Two-variable numeric function approximation using least-squares-based regression

Ultra low-power, -area and -frequency CMOS thyristor based oscillator for autonomous microsystems

Ultra low power on-chip hybrid start-up for wireless sensor networks

An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias

Wide band edge-coupled impedance matching network with quarter wavelength measurement circuit

Proceedings Norchip Conference, 2004.

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