NDLI: Design of a hybrid multicore platform for high performance reconfigurable computing

Content Provider	IEEE Xplore Digital Library
Author	Hussain, W. Hoffmann, H. Ahonen, T. Nurmi, J.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Tampere Univ. of Technol., Tampere, Finland (Hussain, W.; Ahonen, T.; Nurmi, J.) \|\| Dept. of Comput. Sci., Univ. of Chicago, Chicago, IL, USA (Hoffmann, H.)
Abstract	This paper presents a loosely-coupled, hybrid architecture of homogeneous and heterogeneous cores integrated together over a Network-on-Chip (NoC). The architecture efficiently utilizes the NoC bandwidth by keeping a balance between the instantiated number of computational and communication nodes. Furthermore, the architecture also provides a mixed flavor of homogeneous general-purpose processing and heterogeneous reconfigurable computing. Prior approaches have mostly considered homogeneous and heterogeneous platforms as two different design paradigms despite both show domain-specific performance advantages over each other. In this context, the proposed architecture is designed for nine NoC nodes, arranged in a topology of three rows and three columns. The middle row contains three homogeneous Reduced Instruction Set Computer (RISC) cores and rest of the nodes are integrated with Coarse-Grain Reconfigurable Arrays (CGRAs) of application-specific sizes. The overall architecture is template-based which can be crafted to application's performance requirements. The NoC allows loose coupling, so all the cores can mutually exchange the data as well as enable independent and simultaneous execution. Contrarily, the user can program the middle layer of RISC cores for specific data/control dependencies among all the cores. The system mitigates power dissipation as the CGRAs are custom tailored for heterogeneous computing. The platform is evaluated for a proof-of-concept test comprising of massively-parallel signal processing algorithms. Synthesis results from a Field Programmable Gate Array device are used to establish comparisons and evaluation against some of the existing state-of-the-art multicore platforms in terms of multiple performance metrics.
Starting Page	1
Ending Page	8
File Size	1018709
Page Count	8
File Format	PDF
e-ISBN	9781467365765
DOI	10.1109/NORCHIP.2015.7364376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-26
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Three-dimensional displays Multicore processing Switches Power dissipation Synchronization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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