NDLI: Simulation of thermal behavior for Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Wegner, T. Cornelius, C. Gag, M. Tockhorn, A. Uhrmacher, A.
Copyright Year	2010
Description	Author affiliation: Institute of Applied Microelectronics and Computer Engineering, University of Rostock, Richard-Wagner-Str. 31, 18119 Warnemuende, Germany (Wegner, T.; Cornelius, C.; Gag, M.; Tockhorn, A.; Uhrmacher, A.)
Abstract	Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a system's thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2×2 NoC, for example.
Starting Page	1
Ending Page	4
File Size	172813
Page Count	4
File Format	PDF
ISBN	9781424489725
e-ISBN	9781424489732
e-ISBN	9781424489718
DOI	10.1109/NORCHIP.2010.5669472
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-15
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Temperature measurement Temperature sensors Computational modeling Thermal resistance Integrated Circuits Network-on-Chip Temperature Modeling Mathematical model System-on-a-chip Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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