NDLI: Ring road NoC architecture

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2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)

Proceedings Norchip Conference, 2004.

Table of contents

Millimetre wave metamorphic HEMT amplifiers

A broad-band quadrature-modulator in standard 0.13μm CMOS

Ring road NoC architecture

Low-power and error coding for network-on-chip traffic

A low-power CMOS front-end for cuff-recorded nerve signals

A CMOS analog integrated circuit for actuation and readout of a MEMS $CO_{2}$ sensor

A linear capacitive sensor interface circuit with single-ended to differential output capability

An inductorless peaking technique applied to MOS current-mode logic gates

Silicon self-switching-device based logic gates operating at room temperature

Multifunction subthreshold gate used for a low power full adder

A 0.6 v 1.6 mW fully integrated voltage- controlled oscillator in 90 nm CMOS aiming for the GPS L1 band

Injection locked coupled VCOs for low phase noise and high accuracy quadrature generation

A novel 1V-supply, low power, wide tuning range voltage controlled oscillator implemented in 0.18/spl mu/m CMOS technology

FPGA based fault emulation of synchronous sequential circuits

Efficient image filtering and information reduction in reconfigurable logic

An analysis of the embedded system design space and two case studies, replacing uP's with an FPGA

Implementation experiments of analog nonvolatile memory with a standard 0.35 μ m CMOS

Bridging concurrent and non-concurrent error detection in FIR filters

A novel approach for implementation of adaptive learning rate neural networks

Efficient behavioral modeling of small timing errors in A/D and D/A converters

Analytical expression of the efficiency of phantom zero compensation applied on negative-feedback amplifiers

Analysis method of nonlinear self-heating ef fects based on simulated large signal spectra

Histogram based background correction of ADC

Programmable analog integrated circuit

Low-power reconfigurable baseband block for UMTS/WLAN transmitters

Design criteria for the RF section of long range passive RFID systems

A method of varactor capacitance modulation reduction in CMOS LC-VCOs

Comparison of different class-D power amplier topologies for 1-bit band-pass delta-sigma D/A converters

A modified shield-based test fixture for silicon-on-insulator (SOI) to mitigate the uncertainties of the parallel parasitics

Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies

Impact of oscillator power in discrete and continuous time /spl Sigma//spl Delta/ converters

Multistandard receiver for home networking and digital media

Improving a network security system by recongurable hardware

Power analysis of high throughput pipelined carry-propagation adders

High-speed on-chip interconnect modeling for circuit simulation

Phase noise analysis of the LC-tank CMOS oscillator

A phase noise analysis of CMOS colpitts oscillators

Low-phase-error and low-phase-noise 2GHz CMOS quadrature VCOs

Baseband digital predistorter with quadrature error correction

Improving multiple-branch FIR filter structures through constrained optimization

A new class of linear-phase FIR filters based on switching and resetting of IIR filters

A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR

A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation

A low-power reconfigurable analog filter for UMTS/WLAN receivers

Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology

Dynamic element matching in decomposed digital-to-analog converters

0.25μ m CMOS analog multiplier for polynomial predistorter

A Σ Δ fractional-N closed-loop modulator for DECT

A tool for low-power synthesis of FSMs with mixed synchronous/asynchronous state memory

Implementation of a self-timed asynchronous parallel FIR filter using CSCD

Integrated time counter with 200 ps resolution

Power consumption estimation of the multi-threaded xinc processor

A variable word-width content addressable memory for fast string matching

μ spider: a CAD tool for efficient NoC design

A simulation model for embedding the transistor bias

A UML pro le for the TACO protocol processing platform

Communication scheme for an advanced java co-processor

A single chip 802.11 a/b/g WLAN transceiver

A SW-HW implementation of arbitration protocols

A DC-13GHz LNA for UWB RFID applications

An analog current-mode 2-D DCT implementation

First measurement results of a gray-code current-mode ADC

13.5 MHz class-S modulator for an EER transmitter

Improving capacitive drive capability of miller compensated amplifier

A low power, propagation delay stable, continuous-time comparator

On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system

Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip

Flit ejection in on-chip wormhole-switched networks with virtual channels

Radio design for future wireless soc platforms- an overview

RF requirements for multi-hop cellular network repeaters

An RF CMOS Q-enhanced LC resonator

A 1 GHz AGC amplifier in BiCMOS with 3 μ s settling-time for 802.11a WLAN

Formal timing model for hardware components

An improved estimation methodology for hybrid BIST cost calculation

Memory hierarchy usage estimation for global loop transformations

Yield enhancement techniques in analog design automation

Ring road NoC architecture

Content Provider	IEEE Xplore Digital Library
Author	Samuelsson, H. Kumar, S.
Copyright Year	2004
Description	Author affiliation: School of Engineering, Jonkoping University, Department of ElectronidComputer Engineering, P.O. Box 1026, S-551 11 Jonkoping, Sweden (Samuelsson, H.; Kumar, S.)
Abstract	A network of routers on a chip which allows packet switched communication, referred as Networks on Chip (NoC). provides a scalable interconnection architectural option for rapid development of Sacs. In this paper we describe a new NoC architecture. called Ring Road NoC $(R^{2}NoC),$ which was motivated by smooth flow of traffic in interconnected ring roads. Router design and routing algorithm for $R^{2}NoC$ is much simpler. We have developed a SystemC model of $R^{2}NoC$ and our simulation studies demonstrate that the proposed architecture leads to smooth and evenly distributed flow of communication traffic.
Starting Page	16
Ending Page	19
File Size	334889
Page Count	4
File Format	PDF
ISBN	0780385101
DOI	10.1109/NORCHP.2004.1423811
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-08
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packet switching Network topology Roads Network-on-a-chip Integrated circuit interconnections Telecommunication traffic Traffic control Routing Throughput Communication switching
Content Type	Text
Resource Type	Article

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