NDLI: Implementation and Research on EHW-based Digital Chip Using Handel-C Language

Content Provider	IEEE Xplore Digital Library
Author	Qian-sheng Fang Yi Yang Wan-li Chen Li-jun Wang
Copyright Year	2007
Description	Author affiliation: Anhui Inst. of Archit. & Ind., Hefei (Qian-sheng Fang; Yi Yang; Wan-li Chen; Li-jun Wang)
Abstract	When conventional electronic design automation (EDA) technology is used to design digital chip, there are many stubborn difficulties such as being unable to automatically repair if hardware malfunctions, being lack of adaptation etc. However, evolvable hardware (EHW) can adapt to different environment and enhance its performance since it is capable of self-organization, self- adaptation and self-repair. Handel-C Language, having its origin in ISO/ANSI-C programming language, as well as lots of reusable routine C programs, can execute on field programmable gate array (FPGA), so, in a very real sense, hardware implementation is performed completely by means of software. The present paper selects six-multiplexor as the target circuit, and the digital chip with evolutionary function is successfully implemented. Also, an approach to design digital chip with the ability to automatically repair is presented, and some key problems in the process of hardware implementation are solved. The simulated experiment verifies that the presented approach has great evolutionary efficiency and the designed chip has to some degree the ability of self-repair.
Starting Page	624
Ending Page	628
File Size	264437
Page Count	5
File Format	PDF
ISBN	9780769528755
DOI	10.1109/ICNC.2007.436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Computer languages Electronic design automation and methodology ISO Circuit simulation Evolutionary computation Software performance Hardware design languages Software tools Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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