NDLI: On modeling and optimizing cost in 3D Stacked-ICs

Content Provider	IEEE Xplore Digital Library
Author	Taouil, M. Hamdioui, S. Marinissen, E.J.
Copyright Year	2011
Description	Author affiliation: Computer Engineering Lab, Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands (Taouil, M.; Hamdioui, S.) \|\| IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium (Marinissen, E.J.)
Abstract	3D-Stacked IC (3D-SIC) technology is one of the emerging technologies with many benefits such as higher performance and heterogeneous integration. During the manufacturing of such ICs, tests can be applied at different moments such as (a) before the stacking process, (b) after the creation of each partial stacked IC, (c) after the creation of the complete stack, and (d) after packaging of the stack. Moreover, each applied test may target interconnects, one or more dies, or even both. This results into a huge number of test flows, each with its own specific test cost. Choosing an efficient and appropriate test flow providing the required outgoing product quality (for a given design and manufacturing parameters) is extremely important in order to make 3D-SIC business profitable. This paper discusses a tool for 3D-SIC test cost modeling; It gives the requirements and classifies them in design, manufacturing, test, packaging and logistics. It further covers user-cases and shows how the tool can be used at an early design stage in order to select the most efficient test flow for given input parameters (related either to manufacturing, test, packaging or logistics); hence, optimize the design and/or include the required DFT to support the selected test flow. The tool can be also used for sensitivity analysis where the impact of parameter changes on the test cost can be analyzed.
Starting Page	24
Ending Page	29
File Size	480631
Page Count	6
File Format	PDF
ISBN	9781467304689
ISSN	2162061X
e-ISBN	9781467304696
e-ISBN	9781467304672
DOI	10.1109/IDT.2011.6123096
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-11
Publisher Place	Lebanon
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	3D Test Cost Stacking Through-Silicon-Via Companies Packaging 3D Manufacturing Cost Three dimensional displays Manufacturing 3D Test Flows Testing Logistics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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