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Content Provider | IEEE Xplore Digital Library |
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Author | Youness, H. Hussein, A. Mahfoz, A. |
Copyright Year | 2015 |
Description | Author affiliation: Comput. & Syst. Eng, Minia Univ., Egypt (Youness, H.; Hussein, A.) || Electr. Eng., High Inst. of Eng. & Technol., Minia, Egypt (Mahfoz, A.) |
Abstract | Hardware/software (HW/SW) partitioning is one of the most important issues of co-design systems, deciding which components of the system could be implemented in hardware and which ones in software. It plays a crucial role in improving the system performance. HW/SW partitioning problem is also a NP-hard problem. In this paper, a new hardware/software partitioning technique is presented to reduce the overall execution time of the system; the technique is based on dividing the task graphs into levels. In each level, the task with high computing cost and high communication cost is assigned to hardware implementation. If there is no task with the previous specifications, the technique computes granularity of each task, for the task with coarse grain is assigned to hardware implementation. Experimental results conclude that the proposed algorithm is an efficient algorithm to reduce the overall execution time and reduce hardware resources about 45% to the existing one. |
Sponsorship | Ain Shams Univ. |
Starting Page | 113 |
Ending Page | 118 |
File Size | 186489 |
Page Count | 6 |
File Format | |
e-ISBN | 9781467399715 |
DOI | 10.1109/ICCES.2015.7393030 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-12-23 |
Publisher Place | Egypt |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Algorithm design and analysis Co-design Partitioning Software algorithms Task graph Hardware Software Scheduling Partitioning algorithms Time complexity algorithm |
Content Type | Text |
Resource Type | Article |
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