NDLI: Efficient search area loading technique for block-based motion estimation and its FPGA implementation using flexible triangle search algorithm

Content Provider	IEEE Xplore Digital Library
Author	Rehan, M. Nashed, R.
Copyright Year	2009
Description	Author affiliation: Department of electrical and communications engineering, British University in Egypt (Rehan, M.) \|\| Department of electrical and communications engineering, the British University in Egypt (Nashed, R.)
Abstract	An efficient technique for loading search area in block-based motion estimation is proposed. The main advantage of the proposed technique is to reduce number of search area loading cycles by taking advantage of the vertical and horizontal overlap between adjacent search areas and thus improve the overall performance of the motion search and frame encoding. The proposed technique was implemented in FPGA as part of the flexible triangle search (FTS) motion estimation algorithm. However, the proposed technique can be used in similar search algorithm. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work. The FTS can be used for block-based motion estimation where it can locate the best matching blocks between two frames using a search triangle that changes its direction and its size through a set of operations. These operations provide the triangle with the large flexibility to locate the best matching block in less number of search iterations. Simulation results indicates that the proposed technique reduces number of cycles required for motion estimation by around 8% and thus enable the video encoder to support higher frequencies or larger resolutions. The proposed design was implemented, simulated, and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the FTS algorithm published in previous work.
Starting Page	33
Ending Page	36
File Size	121623
Page Count	4
File Format	PDF
ISBN	9781424458424
DOI	10.1109/ICCES.2009.5383314
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Video coding Concurrent computing Motion estimation Computer architecture Hardware Encoding Frequency estimation video coding Field programmable gate arrays FPGA design Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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