NDLI: A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR

Content Provider	IEEE Xplore Digital Library
Author	Obermaisser, R. Kraut, H. Salloum, C.
Copyright Year	2008
Description	Author affiliation: Vienna Univ. of Technol., Vienna (Obermaisser, R.; Kraut, H.; Salloum, C.)
Abstract	The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satisfactorily with increasing transistor counts. In conjunction with the increasing rates of transient faults in logic and memory associated with the continuous reduction of feature sizes, this situation creates the need for novel MP- SoC architectures. This paper introduces such an architecture, which supports the integration of multiple, heterogeneous IP cores that are interconnected by a time-triggered Network-on-a-Chip (NoC). Through its inherent fault isolation and determinism, the proposed MPSoC provides the basis for fault tolerance using Triple Modular Redundancy (TMR). On-chip TMR improves the reliability of a MPSoC, e.g., by tolerating a transient fault in one of three replicated IP cores. Off-chip TMR with three MPSoCs can be used in the development of ultra-dependable applications (e.g., X-by-wire), where the reliability requirements exceed the reliability that is achievable using a single MPSoC. The paper quantifies the reliability benefits of the proposed MPSoC architecture by means of reliability modeling. These results demonstrate that the combination of on-chip and off- chip TMR contributes towards building more dependable distributed embedded real-time systems.
Starting Page	123
Ending Page	134
File Size	420637
Page Count	12
File Format	PDF
ISBN	9780769531380
DOI	10.1109/EDCC-7.2008.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-07
Publisher Place	Lithuania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems system architectures Redundancy dependability Circuit faults Yarn Fault tolerance Voting Logic circuits Network-on-a-chip real-time systems Computer architecture TMR System-on-a-chip
Content Type	Text
Resource Type	Article

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