NDLI: Watermarking Technique for HDL-based IP Module Protection

Content Provider	IEEE Xplore Digital Library
Author	Min-Chuan Lin Guo-Ruey Tsai Chun-Rong Wu Ching-Hui Lin
Copyright Year	2007
Description	Author affiliation: Kun Shan Univ., Tainan (Min-Chuan Lin; Guo-Ruey Tsai; Chun-Rong Wu; Ching-Hui Lin)
Abstract	Reuse-based intellectual property (IP) design is one of the most promising techniques to take the SoC design quickly into market. To facilitate better IP reuse, it is desirable to have IP exchanged in the software form such as hardware description language (HDL) source codes. However, soft IP has higher protection requirements than hard IP, and most existing hard IP protection techniques are not applicable to soft IP. Here, we propose two practical schemes for HDL code protection by inherent characteristic of the FPGA, including look-up table (LUT) units and distributed SRAM, which can be properly documented and synthesizable for reuse. For combinational logic system, the LUT components are very suitable for hiding watermarking by assigning some author's signature into unused logic states. For sequential logic system, we use RAM-based finite state machine (FSM) or programmable finite state machine (PSM) to embed the personal watermark. Without changing the original algorithm in the reused device and increasing extra HDL modules, the proposed watermarking technique is suitable for HDL-based reused IP protection.
Starting Page	393
Ending Page	396
File Size	533735
Page Count	4
File Format	PDF
ISBN	9780769529941
DOI	10.1109/IIH-MSP.2007.326
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Authentication Automata Watermarking Digital signal processing Table lookup System-on-a-chip Protection Hardware design languages Circuit testing Logic devices
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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