NDLI: New Input Matching Technique for Cascode LNA in 90 nm CMOS for Millimeter Wave Applications

Content Provider	IEEE Xplore Digital Library
Author	Hasani, J.Y. Kamarei, M. Ndagijimana, F.
Copyright Year	2007
Description	Author affiliation: Univ. of Tehran, Tehran (Hasani, J.Y.; Kamarei, M.)
Abstract	Low noise amplifier optimization in modern CMOS technologies is based on the noise figure minimization, preserving the input power matching. Unfortunately available analysis and design methods incorporating this design method have used very simple transistor model and are not suitable for the design in millimeter wave frequencies. In this paper we present an accurate analysis to calculate the input impedance of the inductively source-degenerated cascode LNA. Based on the analysis results we have developed analytic equations to calculate the input matching components. To compare the proposed input matching with the available ones, we have designed identical 30GHz 5mW LNA circuits, using different input matching methods. The designs have been simulated using the foundry design kit for the STMicroelectornics 90 nm CMOS process. Based on the simulation results the proposed method outperforms the available methods. Finally the circuit designed using the proposed method, has been layed out and simulated in the foundry design kit.
Starting Page	282
Ending Page	285
File Size	273848
Page Count	4
File Format	PDF
ISBN	9781424413072
DOI	10.1109/RFIT.2007.4443971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Millimeter wave transistors Noise figure Low-noise amplifiers Design methodology Circuit simulation Minimization cascode millimeter wave CMOS LNA Impedance matching Millimeter wave technology inductively degenerated CMOS technology Foundries LNA
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

0.18 µm fully integrated 900 MHz CMOS LNA with input and output on-chip matching for multi-standard mobile receiver

A switchable CMOS LNA using capacitor switching

A 0.13µm inductively degenerated cascode CMOS LNA at 2.14GHz

A 130 nm CMOS LNA for 30 GHz applications

A transformer-based 60GHz CMOS LNA for low voltage applications

An RF cascode BJT-LNA with shunt-series input matching

A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

Simulation of single stage cascode low noise amplifier at 5.8GHz using t-matching network

New Input Matching Technique for Cascode LNA in 90 nm CMOS for Millimeter Wave Applications

Similar Documents

0.18 µm fully integrated 900 MHz CMOS LNA with input and output on-chip matching for multi-standard mobile receiver

A switchable CMOS LNA using capacitor switching

A 0.13µm inductively degenerated cascode CMOS LNA at 2.14GHz

A 130 nm CMOS LNA for 30 GHz applications

A transformer-based 60GHz CMOS LNA for low voltage applications

An RF cascode BJT-LNA with shunt-series input matching

A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

Simulation of single stage cascode low noise amplifier at 5.8GHz using t-matching network

New Input Matching Technique for Cascode LNA in 90 nm CMOS for Millimeter Wave Applications