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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dolecek, L. |
| Copyright Year | 2010 |
| Description | Author affiliation: Electrical Engineering Department, University of California, Los Angeles, Los Angeles, CA, 90095 (Dolecek, L.) |
| Abstract | Emerging non-volatile memory devices show tremendous promise for a wide variety of applications, ranging from consumer electronics to server technologies. The advent of such multi-scale opportunities also carries a unique set of challenges. Increasingly popular Flash memory devices possess an intrinsic asymmetry during the write operation: programming memory cells to values lower than currently stored values is considerably slower and more costly than programming to higher values. It is critical to keep this cost low, as it directly affects memory lifetime and performance. Concurrently, demands for higher densities under reduced technology sizing make the data reliability a formidable objective. To address the compound issue of sustained and low-cost data reliability and high performance, in this work we propose a methodology to provide guaranteed immunity to a prescribed number of asymmetric errors, while having asymptotically negligible redundancy. Our construction uses ideas from additive and combinatorial number theory, and builds upon recently introduced coding schemes. We first show how this construction can be used in the single level cell (SLC) setup, and subsequently extend the construction to the setting with several levels per cell, including multi-level cell (MLC) and triple-level (TLC) setting. We also discuss practical aspects of such schemes, including methods for systematic encoding, correction of limited-magnitude errors, and the additional protection under a certain number of bidirectional errors. This number-theoretic based approach is a promising direction for extending the lifetime of memories at sustained reliability. |
| Starting Page | 1936 |
| Ending Page | 1940 |
| File Size | 359108 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424488636 |
| e-ISBN | 9781424488650 |
| DOI | 10.1109/GLOCOMW.2010.5700281 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Systematics Redundancy Flash memory Encoding Decoding Indexes Equations |
| Content Type | Text |
| Resource Type | Article |
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