NDLI: Three-Tier Architecture for Resource Selection in Grid

Content Provider	IEEE Xplore Digital Library
Author	Varalakshmi, P. Selvi, S. Thamarai Ashraf, A. Javed Karthick, K. Aarthy, S. Baby
Copyright Year	2007
Abstract	In most of the trust-based systems, intermediaries, known as brokers, are responsible for the selection of Service Providers (SPs) for consumer requests. In such models, the intermediaries gain monetary benefit for each of the transactions made through them. This may lead to favoritism & bias in the selection of suitable SPs. This challenge may be overcome by the proposed three-tier framework where the Regional Resource Administrators (RRAs), resource brokers and the SPs are arranged into three-tiers. RRAs derive their compensation from registration, renewal, and audit charges paid by broker community, not from individual transactions. RRAs serve the consumer community in an `unbiased' and `trustworthy' manner. In this model, the trust-indices of each of the entities are computed based on the feedback provided by other entities after each transaction. These trust-indices of brokers, consumers and SPs are updated dynamically at the RRA's and the broker's sites respectively, to ensure trustworthy services and to quicken the selection of `suitable' SPs. A B-Tree indexing scheme has been proposed to further improve the selection process. Global trust-indices of the SPs are computed using Back Propagation Neural Networks, further quickens the selection of a `suitable' SP. Our model shows a marked improvement in job-success-rate for various percentages of malicious entities. The selection query- cost for each transaction is reduced using B-Tree thereby improving the selection response.
Starting Page	559
Ending Page	566
File Size	692984
Page Count	8
File Format	PDF
ISBN	0769530591
DOI	10.1109/ADCOM.2007.44
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-18
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Integrated circuit technology Digital integrated circuits Very large scale integration Silicon Pins Circuit testing Integrated circuit reliability Digital filters Analog integrated circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Radiated emissions of very large scale integrated circuits

Three-dimensional integration: technology, use, and issues for mixed-signal applications

Isolating analog circuits from digital interferences

Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design

Potential of MOS Technologies for Analog Integrated Circuits

Fault model for VLSI circuits reliability assessment

Analog IC Design in Nanometer CMOS Technologies

Challenges in Testing of Mixed Mode Analog/Digital ICs

A syndrome signature for exhaustive testing of combinational circuits

Three-Tier Architecture for Resource Selection in Grid

Similar Documents

Radiated emissions of very large scale integrated circuits

Three-dimensional integration: technology, use, and issues for mixed-signal applications

Isolating analog circuits from digital interferences

Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design

Potential of MOS Technologies for Analog Integrated Circuits

Fault model for VLSI circuits reliability assessment

Analog IC Design in Nanometer CMOS Technologies

Challenges in Testing of Mixed Mode Analog/Digital ICs

A syndrome signature for exhaustive testing of combinational circuits

Three-Tier Architecture for Resource Selection in Grid