NDLI: Ant Colony Optimization and its Application to Boolean Satisfiability for Digital VLSI Circuits

Content Provider	IEEE Xplore Digital Library
Author	Sethuram, R. Parashar, M.
Copyright Year	2006
Description	Author affiliation: Rutgers Univ., Piscataway (Sethuram, R.; Parashar, M.)
Abstract	Ant colony optimization (ACO) [8] is a non-deterministic algorithm framework that mimics the foraging behavior of ants to solve difficult optimization problems. Several researchers have successfully applied ACO framework in different fields of engineering, but never in VLSI testing. In this paper, we first describe the basics of the ACO framework and ways to formulate different optimization problems within an ACO framework. We then present our own ACO algorithm to simultaneously solve multiple boolean SAT instances for digital VLSI circuits. Experiments conducted on scanned versions of ISCAS'89 benchmark circuits produced astonishing results. ACO framework for boolean satisifiability was found 200 times faster than spectral meta-heuristics [36] run in combinational mode. ACO framework has proven to be a promising optimization technique in large number of other fields. Since ACO can be used to solve different types of optimization and search problems, we believe that the concepts presented in this paper can open the gates for researchers solving different optimization problems that exist in VLSI testing more efficiently.
Starting Page	507
Ending Page	512
File Size	213678
Page Count	6
File Format	PDF
ISBN	142440715X
DOI	10.1109/ADCOM.2006.4289945
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-20
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software testing Ant colony optimization Sequential analysis Insects Very large scale integration Benchmark testing Search problems Routing Application software Circuit testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Application of Improved Ant Colony Algorithm in Integrated Circuit Routing

Ant Colony Optimization and its Application to Boolean Satisfiability for (2007)

Retiming algorithms with application to VLSI testability

Test Set Optimization Based on Intelligent Hybrid Algorithm

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system

A Fast Algorithm for VLSI Building Block Placement

A novel ACO-based pattern generation for peak power estimation in VLSI circuits

Adaptive Diagnostic Pattern Generation for Scan Chains

Ant Colony Optimization and its Application to Boolean Satisfiability for Digital VLSI Circuits

Similar Documents

Application of Improved Ant Colony Algorithm in Integrated Circuit Routing

Ant Colony Optimization and its Application to Boolean Satisfiability for (2007)

Retiming algorithms with application to VLSI testability

Test Set Optimization Based on Intelligent Hybrid Algorithm

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system

A Fast Algorithm for VLSI Building Block Placement

A novel ACO-based pattern generation for peak power estimation in VLSI circuits

Adaptive Diagnostic Pattern Generation for Scan Chains

Ant Colony Optimization and its Application to Boolean Satisfiability for Digital VLSI Circuits