NDLI: An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs

Content Provider	IEEE Xplore Digital Library
Author	Holsmark, R. Kumar, S.
Copyright Year	2011
Abstract	New techniques and tools will be required to handle the complexity of on-chip networks required for building multi-core platforms with hundreds of cores. The concepts of hierarchy and abstraction, which have been useful in the design and analysis of electronic systems, will also be useful in the network design area. In this paper we propose an abstraction for networks to reduce the complexity of design and analysis of deadlock-free routing for large and hierarchical networks. Raising the level of abstraction necessarily leads to loss of some information. This loss of information in turn often results in loss of performance of the design as compared to when the network was considered at a lower level of abstraction. We show that our proposed abstraction leads to very small loss of performance. In particular, we show that average increase in communication distance (hops) is low or comparable to non-abstract design. Our simulation-based evaluation indicates that abstract routing design has no negative impact on message latency. On the contrary, abstract routing shows a slight advantage, which increases if more network communication is local and confined within subnets.
Starting Page	59
Ending Page	66
File Size	1111804
Page Count	8
File Format	PDF
ISBN	9781457703836
DOI	10.1109/CIT.2011.32
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-31
Publisher Place	Cyprus
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Network topology Deadlock Free Routing System recovery Routing Concrete Topology Networks on Chip Network Analysis Joining processes Hierarchical Networks
Content Type	Text
Resource Type	Article

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