NDLI: Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip

Content Provider	IEEE Xplore Digital Library
Author	Li-ke Yan Yuan Wen Man Cao Tian-zhou Chen De-gui Feng
Copyright Year	2010
Abstract	In recent years, special attention has been paid to slot-based reconfigurable devices interconnected by NoCs (networks on chip). An urgent problem is how one reallocatable task can communicate with others. This paper proposes two approaches to augment NoC for slot-based reconfigurable system by adding a naming module to solve this problem. In the first approach, the naming module is outside of the mesh and connects to each slot using a dedicated channel. In the second approach, the naming module is inside the mesh and communicates with other slots using NoC routing. As for the results, for the best situation in a 16x16 mesh, average delay increases by 1.15% and by 6.00% for over-network mode and in-network mode respectively. These two average delays would increase with increasing reconfiguration rate, with the increase for the in-network mode being faster than that for the over-network mode. And the decrease of throughput is negligible in both modes.
Starting Page	2300
Ending Page	2305
File Size	433176
Page Count	6
File Format	PDF
ISBN	9781424475476
e-ISBN	9781424475483
DOI	10.1109/CIT.2010.396
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-29
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	dynamic partial reconfiguration Microprocessors Computer architecture network on chip Throughput Delay Field programmable gate arrays Indium phosphide naming service Load modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Optimizing Partial Reconfiguration of Multi-context Architectures

Survey of Dynamically Reconfigurable Network-on-Chip

rrBox: A remote dynamically reconfigurable network processing middlebox

Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks

SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications

A dynamic partial reconfigurable FIR filter architecture

Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip

Similar Documents

An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Optimizing Partial Reconfiguration of Multi-context Architectures

Survey of Dynamically Reconfigurable Network-on-Chip

rrBox: A remote dynamically reconfigurable network processing middlebox

Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks

SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications

A dynamic partial reconfigurable FIR filter architecture

Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration

Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip