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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiaohuang Huang Rodrigues, C.I. Jones, S. Buck, I. Wen-mei Hwu |
| Copyright Year | 2010 |
| Abstract | There are two avenues for many-core machines to gain higher performance: increasing the number of processors, and increasing the number of vector units in one SIMD processor. A truly scalable algorithm should take advantage of both. However, most past research on scalable memory allocators scales well with the number of processors, but poorly with the number of vector units in one SIMD processor. As a result, they are not truly scalable on many-core architectures. In this work, we introduce our proposed solution through the design of XMalloc, a truly scalable, efficient lock-free memory allocator. We will present (1) our solution for transforming traditional atomic compare-and-swap based lock-free algorithm to scale on SIMD architectures, and (2) a hierarchical cachelike buffer solution to reduce the average latency of accesses to non-scalable or slow resources such as main memory in a many-core machine. We implemented XMalloc as a memory allocator on an NVIDIA Tesla C1060 GPU with 240 processing units. Our experimental results show that XMalloc scales very well with growth in both the number of processors and the number of vector units in each SIMD processor. Our truly scalable lock-free solution achieves 211 times speedup compared to the common lock-free solution. |
| Starting Page | 1134 |
| Ending Page | 1139 |
| File Size | 350844 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424475476 |
| e-ISBN | 9781424475483 |
| DOI | 10.1109/CIT.2010.206 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-29 |
| Publisher Place | United Kingdom |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis malloc Instruction sets Scalability lock-free async-signalsafe Data structures availability scalability GPGPU CUDA Memory management Resource management |
| Content Type | Text |
| Resource Type | Article |
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