NDLI: Loop Selection to Boost Thread Level Speculation Parallelism in Chip Multiprocessor Systems

Content Provider	IEEE Xplore Digital Library
Author	Yue Wu Lei Xu Hongbin Yang
Copyright Year	2009
Abstract	A novel loop selection framework with cost evaluation to boost thread level speculation (TLS) parallelism in chip multiprocessor (CMP) systems is proposed in this paper. In order to improve the performance, a loop selection framework with the aid of TLS and profiling is added to reduce unnecessary loops parallelization for their low gains even losses under parallelization. A number of techniques for this parallelization based TLS are presented and results provided indicate the performance contribution on six SPEC CPU2000 benchmark applications. This TLS parallelization yielded an average 175% speedup on our three integer applications and an average 198% on our three floating point applications.
Starting Page	249
Ending Page	253
File Size	265109
Page Count	5
File Format	PDF
ISBN	9780769538365
DOI	10.1109/CIT.2009.42
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs thread level parallelism thread level speculation Performance gain loop selection Yarn Information technology Multiprocessing systems Concurrent computing Parallel processing System recovery Writing chip multiprocessor Performance loss automatic parallelization
Content Type	Text
Resource Type	Article

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Loop Selection to Boost Thread Level Speculation Parallelism in Chip Multiprocessor Systems