NDLI: Performance Modeling of Emerging HPC Architectures

Content Provider	IEEE Xplore Digital Library
Author	Bhatia, N. Alam, S.R. Vetter, J.S.
Copyright Year	2006
Description	Author affiliation: Comput. Sci. & Math. Div., Oak Ridge Nat. Lab., TN (Bhatia, N.; Alam, S.R.; Vetter, J.S.)
Abstract	Current state-of-art HPCMP performance modeling techniques primarily rely on combining a performance profile of an application on a well-known HPC architecture, and the machine characteristics of an emerging architecture to project an application's performance on the emerging architecture. Existing profiling and tracing tools on well-known architectures are typically used to collect the necessary performance data by executing applications and benchmarks on available systems. Since the performance enhancing features of novel processing devices may be significantly different from a conventional microprocessor system, current performance modeling schemes have limited applicability on systems like the Cray X1E vector supercomputer and parallel systems with accelerator devices like Cray XD1, which contains FPGAs. We employ an application modeling paradigm that allows a user to develop not only "architecture aware" but also "application aware"performance models. We extend the modeling assertions (MA) framework that permits a user to develop multi-resolution, parameterized symbolic models. We demonstrate the application of our modeling scheme by augmenting the MA models with performance enhancing attributes of the Cray X1E Multistrearning Processors (MSPs). Using the extended MA framework, we develop symbolic performance models of critical code blocks of an HPCMP 71-06 benchmark called HYCOM - an ocean modeling code. By representing the code characteristics of the critical code blocks in terms of both unique architectural attributes and key input parameters of the HYCOM application, we manage to reduce and sustain performance prediction error rates to less than 30%
Sponsorship	HPCMPO Outreadh Team US DoD DoD HPC UGC
Starting Page	367
Ending Page	373
File Size	383875
Page Count	7
File Format	PDF
ISBN	0769527973
DOI	10.1109/HPCMP-UGC.2006.58
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer science Runtime Oceans Memory management Computer architecture Predictive models Supercomputers Mathematics Mathematical model Application software
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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