NDLI: VSIPL++ Acceleration Using Commodity Graphics Processors

Content Provider	IEEE Xplore Digital Library
Author	Campbell, D.
Copyright Year	2006
Description	Author affiliation: Sensors & Electromagn. Applications Lab., Georgia Tech Res. Inst., Smyrna, GA (Campbell, D.)
Abstract	The High Performance Embedded Computing Software Initiative (HPEC-SI) is developing a unified software framework for computation and communication for high performance signal processing tasks on parallel computers. The goal of the program is to address the high cost of software in Department of Defense (DoD) systems by improving the portability and productivity of signal processing application development, while simultaneously improving performance compared to current practices. The Vector, Signal, and Image Processing Library (VSIPL) is a portable application programming interface (API) that is widely used for embedded DoD signal processing systems. One portion of the HPEC-SI effort includes the development of C++ extensions for the existing VSIPL standard, called VSIPL++. Commodity graphics processing units (GPUs) are application-specific processors that implement a standardized three-dimensional graphics-rendering pipeline, and provide significant floating-point processing capacity at much lower cost, power consumption, and physical space compared to general-purpose processors. Recent changes in GPUs have increased programmability and flexibility in portions of the rendering pipeline, allowing non-graphics applications to exploit their computational capacity. Restrictions on the programming model, lack of appropriate tools, unusual performance behavior, and other factors make exploiting GPUs a costly, difficult, and time-consuming process for application developers. The embedded systems that VSIPL and VSIPL++ are commonly used on share several important characteristics with GPUs, making VSIPL++ well suited to abstract and exploit GPUs. This paper describes GPUVSIPL++, an implementation of portions of the VSIPL++ standard that exploits a GPU to accelerate computation beyond what is possible on a development workstation
Sponsorship	HPCMPO Outreadh Team US DoD DoD HPC UGC
Starting Page	315
Ending Page	320
File Size	285844
Page Count	6
File Format	PDF
ISBN	0769527973
DOI	10.1109/HPCMP-UGC.2006.77
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics Concurrent computing Embedded computing Costs High performance computing Software performance Signal processing Acceleration Application software Embedded software
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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