NDLI: Implementation of code acquisition and code tracking loop for CDMA wireless local loop system

Content Provider	IEEE Xplore Digital Library
Author	Jae-Wook Chung Jin-Su Kim Young-Gyun Jeong Jeong-Suk Ha
Copyright Year	1998
Description	Author affiliation: Electron. & Telecommun. Res. Inst., Daejeon, South Korea (Jae-Wook Chung)
Abstract	The wireless local loop (WLL) system has been deployed as a new application for wireless communication with fixed subscriber units which impose a fixed propagation and no handoffs compared to the wireless mobile communication systems. The design of the WLL system is much simpler than that of a mobile system because no handoff occurs in a fixed-to-fixed link. This paper describes hardware design and the implementation of the code acquisition module and code tracking loop module of the base station receiver for the code division multiple access (CDMA) WLL system proposed by the Electronics and Telecommunications Research Institute (ETRI). These modules of the CDMA WLL system are implemented by hardware chips, such as digital signal processors (DSP), erasable programmable logic devices (EPLD), and field programmable gate arrays (FPGA). Timing simulation of the implemented system is operated using the ALTERA MAXPLUS tool. The basic hardware modules of the base station receiver consist of two searchers for antenna diversity and four fingers for multi-path combining. We verify the operation of the code acquisition and time tracking loop on the call test. The reconstructed voice data show good quality in the reverse link. It will be possible to implement an ASIC design in the use of this code acquisition and code tracking loop module.
Starting Page	1204
Ending Page	1208
File Size	533683
Page Count	5
File Format	PDF
ISBN	0780343204
ISSN	10903038
DOI	10.1109/VETEC.1998.686430
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-21
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tracking loops Multiaccess communication Hardware Wireless communication Base stations Field programmable gate arrays Programmable logic arrays Diversity reception Mobile communication Digital signal processors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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