NDLI: Implementation of base station receiver for CDMA wireless local loop system

Content Provider	IEEE Xplore Digital Library
Author	Chung, J.W. Kim, J.S. Jeong, Y.G. Ha, J.S.
Copyright Year	1997
Description	Author affiliation: Electron. & Telecommun. Res. Inst., Taejon, South Korea (Chung, J.W.)
Abstract	The wireless local loop (WLL) system has been deployed as a new application for wireless communication with fixed subscriber units which impose a fixed to fixed propagation and no handoffs compared to the wireless mobile communication systems. The design of the WLL system is much simpler than that of a mobile system because no handoff occurs in a fixed-to-fixed link. This paper describes the hardware design and implementation of base station receiver for code division multiple access (CDMA) WLL system proposed by Electronics and Telecommunications Research Institute (ETRI). This base station demodulator module of the WLL system is implemented by hardware chips, such as a digital signal processor (DSP), erasable programmable logic device (EPLD), and a field programmable gate array (FPGA). Timing simulation of the implemented system is operated using the ALTERA MAXPLUS tool. The basic hardware modules of the base station receiver consist of two searchers for antenna diversity and four fingers for multipath combining. We verify the operation of the code acquisition and time tracking loop on the call test. The reconstructed speech shows a good quality in the reverse link.
Starting Page	371
Ending Page	374
File Size	526602
Page Count	4
File Format	PDF
ISBN	0780342984
DOI	10.1109/ICPWC.1997.655544
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-12-17
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Base stations Multiaccess communication Hardware Wireless communication Field programmable gate arrays Programmable logic arrays Diversity reception Mobile communication Demodulation Digital signal processors
Content Type	Text
Resource Type	Article

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