NDLI: Identification of high power consuming areas with gate type and logic level information

Content Provider	IEEE Xplore Digital Library
Author	Miyase, K. Sauer, M. Becker, B. Wen, X. Kajihara, S.
Copyright Year	2015
Description	Author affiliation: Kyushu Inst. of Technol., Iizuka, Japan (Miyase, K.; Wen, X.; Kajihara, S.) \|\| Univ. of Freiburg, Freiburg, Germany (Sauer, M.; Becker, B.)
Abstract	Power-related problems in at-speed scan testing have become more and more serious, since excessive IR-drop caused by excessive power consumption results in overtesting. There are two important factors in low-power testing: one is power estimation, the other is power reduction. Several estimation methods have been proposed based on the analysis of switching activity characteristics. In order to estimate the impact of IR-drop, it is more important to consider the area containing many cells which consume excessive power than to consider the total number of switching activity in a circuit. In this paper, we propose a novel method for identifying areas where excessive IR-drop likely occurs without using test vectors. Visualized experimental results for IWLS 2005 benchmark circuits demonstrate that the proposed method can effectively identify areas containing many cells which consume higher power than others. Such areas identified can be used in low-power test generation so as to achieve effective and efficient results.
Starting Page	1
Ending Page	6
File Size	577934
Page Count	6
File Format	PDF
ISBN	9781479976034
DOI	10.1109/ETS.2015.7138773
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-25
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Switches Power demand Layout Circuit faults Delays Testing test generation power estimation layout design low-power testing
Content Type	Text
Resource Type	Article

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