NDLI: Quantified contribution of design for manufacturing to yield at 28nm

Content Provider	IEEE Xplore Digital Library
Author	Herrmann, T. Malik, S. Madhavan, S.
Copyright Year	2014
Description	Author affiliation: Yield Manage. Solutions, GLOBALFOUNDRIES, Dresden, Germany (Herrmann, T.) \|\| DFM CAD, GLOBALFOUNDRIES, Santa Clara, CA, USA (Malik, S.; Madhavan, S.)
Abstract	Yield is the single most important criterion which drives the economics of our industry, impacting the bottom line directly. It is a well understood fact that both foundries and fabless companies have an extremely strong interest in achieving high yield as quickly as possible to meet the economies of scale and rapid time to market. At the 28nm node and below, implementation of DFM is believed to be particularly critical to enable a fast yield ramp. Quantification of the yield impact of various DFM enhancements is crucial to drive the appropriate design tradeoffs. In this paper we present an analysis of yield impact of DFM features over the duration of technology and product yield ramp for the 28nm node. Yield has inherent variation due to nature of its dependency on multiple factors and stages which makes it difficult to attribute yield signal to a small action in a long chain of event, from design to fabrication, leading to successful yield. We created a set of designs in 28nm, with and without DFM, where DFM changes were done only opportunistically. After finishing these designs, both the unmodified and the DFM enhanced layouts were placed side by side on the test chip reticles. Both instances got tested over long time for yield evaluation on silicon to create enormous amount of data which we analyzed and present in this paper. For analysis of all this data, we compare different statistical methods to understand the same and present challenges faced using these methods. We conclude with successful application of Matched Pair statistical method that quantified yield sensitivity to the DFM design changes.
Sponsorship	IEEE Counc. Electron. Design Autom.
Starting Page	1
Ending Page	6
File Size	1476259
Page Count	6
File Format	PDF
ISBN	9781479934157
DOI	10.1109/ETS.2014.6847815
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-26
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Equations Standards Statistical analysis Fitting Layout Silicon Metals 28nm DFM Yield
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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