NDLI: A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Content Provider	IEEE Xplore Digital Library
Author	Wen, X. Miyase, K. Kajihara, S. Furukawa, H. Yamato, Y. Takashima, A. Noda, K. Ito, H. Hatayama, K. Aikyo, T. Saluja, K.K.
Copyright Year	2008
Description	Author affiliation: Dept. of CSE, Kyushu Inst. of Technol., Iizuka (Wen, X.; Miyase, K.; Kajihara, S.; Furukawa, H.; Yamato, Y.; Takashima, A.)
Abstract	Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.
Starting Page	55
Ending Page	60
File Size	462586
Page Count	6
File Format	PDF
ISBN	9780769531502
DOI	10.1109/ETS.2008.13
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-25
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Clocks Automatic testing Semiconductor device testing Timing Automatic test pattern generation Costs Circuit faults Delay estimation Indium tin oxide Capture Mode At-Speed Scan Testing Yield Loss Test Relaxation X-Filling
Content Type	Text
Resource Type	Article

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