NDLI: The Role of Test in Circuits Built with Unreliable Components

Content Provider	IEEE Xplore Digital Library
Author	Rubio, A.
Copyright Year	2008
Description	Author affiliation: Tech. Univ. of Catalonia, Barcelona (Rubio, A.)
Abstract	The talk will reconsider the role of the test in new emerging device circuits for CMOS Terascale and further technologies where a high level of redundancy will be present. As far as we are getting close to ultimate CMOS and ulterior new emerging nano-devices technologies the indication made by J. von Neumann in 1950 that errors had to be viewed not as an extraneous accident but as an essential part of the process under consideration caused by natural phenomena is becoming a real fact. It is well accepted that at the same time electronic technology is going into the deep nanoscale the device reliability decreases rapidly. For such future technologies internal electromagnetic coupling or just thermal noise as well as permanent manufacturing defects will cause a loss of reliability and introduce an inherent error probabilistic factor to every component of the system. These deviations motivate new design paradigms. Many of these deviations will be transient in nature, at the same time current computer architecture approaches are reaching their practical limits. In order to build reliable electronics it will be necessary to include fault and defect tolerant schemes through the introduction of massive redundancy. Within this change of scenario, in comparison to conventional deterministic logic circuits these emerging technologies have to face new design and test strategies in order to give support to this probabilistic behavior logic.
Starting Page	3
Ending Page	3
File Size	67590
Page Count	1
File Format	PDF
ISBN	9780769531502
DOI	10.1109/ETS.2008.36
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-25
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing CMOS technology Redundancy Logic circuits Logic testing CMOS process Accidents Nanoscale devices Electromagnetic coupling Rapid thermal processing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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