NDLI: Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence

Content Provider	IEEE Xplore Digital Library
Author	Gent, K. Hsiao, M.S.
Copyright Year	2014
Description	Author affiliation: Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA (Gent, K.; Hsiao, M.S.)
Abstract	Automatic test pattern generation for non-scan sequential circuits is an extremely challenging task. If successful, it can offer many benefits to the EDA community, ranging from manufacturing and functional test to post-silicon validation. High-level test generators often miss the low-level details, thus missing the detection of some gate-level faults. On the other hand, gate-level test generators miss the high-level path traversal knowledge to more effectively traverse the state space. In this work, we present a fine-grain mixed-level test generator that utilizes co-simulation of register-transfer and gate levels to generate high quality vectors. The algorithm, based on an ant colony optimization, targets branch coverage at the RTL and simultaneously attempts to associate rare fault excitations with a sequence of branch activations. By weighting these sequences within the fitness function across the two levels, the algorithm is able to achieve high fault coverage in the presence of deep hard-to-reach states without scan. The result is that the test sequences obtained offer both high branch coverage as well high stuck-at coverage with low computational costs. In particular, for hard-to-test circuits such as the ITC'99 circuit b12, >98% branch coverage and >90% stuck-at coverage are achieved, vastly improving over other state of the art non-scan tools.
Sponsorship	IEEE Comput. Soc.
Starting Page	230
Ending Page	235
File Size	235018
Page Count	6
File Format	PDF
ISBN	9781479960309
ISSN	10817735
DOI	10.1109/ATS.2014.50
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vectors Circuit faults Logic gates Automatic test pattern generation Generators Mathematical model Integrated circuit modeling Mixed Level Test ATPG Ant Colony Optimization Stuck-at Fault Swarm Intelligence RTL Test ITC99 Branch Coverage co-simulation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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